Altera cyclone V Technical Reference page 1171

16-20
Single and Burst Request
Timing
T1
T3 - T6
T7
Single and Burst Request
DMA request timing when a peripheral requests a single and a burst transfer.
Figure 16-5: Single and Burst Request Signaling
Timing
T1
T3
T5
T7 - T10
T11
Related Information
DMAWFP
DMAC Performs Single Transfers for a Burst Request
DMA request timing when a peripheral requests a burst transfer, but the DMAC has insufficient data
remaining in the MFIFO to generate a burst and therefore completes the request using single transfers.
Altera Corporation
The DMAC detects a request for a burst transfer.
The DMAC performs a burst transfer.
The DMAC sets
davalid
complete.
The DMAC detects a request for a single transfer.
The DMAC ignores the single transfer request because the DMA channel thread had
executed a DMAWFP burst instruction.
The DMAC detects a request for a burst transfer.
The DMAC performs a burst transfer.
The DMAC sets
davalid
transfer is complete.
on page 16-49
Description
HIGH and sets
datype[1:0]
Description
HIGH and sets
datype[1:0]
to indicate that the burst transfer is
to indicate that the burst
cv_5v4
2016.10.28
DMA Controller
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