Altera cyclone V Technical Reference page 1173

16-22
Using an Event to Restart DMA Channels
•
dma_IRQ4
•
dma_IRQ5
•
dma_IRQ6
•
dma_IRQ7
The INTEN register is used to enable a
clears the corresponding
programmable and the rest of the register is reserved.
The
dma_irq_abort
tion, refer to the "Aborts" chapter. Once the faulting state is cleared by resetting the DMA, the
dma_irq_abort
The
dma_ecc_corrected_IRQ
System Manager. Once the ECC for the DMA is enabled in the System Manager, these two interrupts are
enabled.
Related Information
Aborts
on page 16-23
Using an Event to Restart DMA Channels
When you program the
tions to restart one or more DMA channels.
DMAC executes DMAWFE before DMASEV
To restart a single DMA channel:
1. The first DMA channel executes
2. The other DMA channel executes
restarting the first DMA channel. The DMAC clears the event, one clock cycle after it executes
You can program multiple channels to wait for the same event. For example, if four DMA channels have all
executed
DMAWFE
channels all restart at the same time. The DMAC clears the event, one clock cycle after it executes
DMAC executes DMASEV before DMAWFE
If the DMAC executes
the DMAC executes
cycle, clears the event and then continues execution of the channel thread.
For example, if the DMAC executes
then the event remains pending. If the DMAC executes the
executes the
1. The DMAC halts execution of the channel 4 thread for one clock cycle.
2. The DMAC clears event 6.
3. The DMAC resumes execution of the channel 4 thread.
4. The DMAC halts execution of the channel 3 thread and the thread stalls while it waits for the next
occurrence of event 6.
Altera Corporation
corresponds to bit 4 of the INTEN and INTCLR register
corresponds to bit 5 of the INTEN and INTCLR register
corresponds to bit 6 of the INTEN and INTCLR register
corresponds to bit 7 of the INTEN and INTCLR register
interrupt. Only bits [7:0] of the INTCLR and INTEN register are
dma_irqN
interrupt is always enabled and asserts during an abort condition. For more informa‐
interrupt is automatically cleared.
and
dma_ecc_uncorrected_IRQ
register to generate an event, you can use the
INTEN
DMAWFE
for event 2, and another DMA channel executes
before another channel executes
DMASEV
. When the DMAC executes
DMAWFE
DMASEV 6
instruction for channel 3, the following actions occur:
DMAWFE 6
interrupt and when a bit in the INTCLR register is set, it
dma_irqN
and then stalls while it waits for the event to occur.
using the same event number generating an event and
DMASEV
DMAWFE
and none of the other threads have executed
DMAWFE 6
are cleared through the dma register in the
and
DMASEV
for event 2, the four DMA
DMASEV
, the event remains pending until
DMAWFE
, it halts execution for one
instruction for channel 4 and then
cv_5v4
2016.10.28
instruc‐
DMAWFE
.
DMASEV
.
DMASEV
clock
aclk
,
DMAWFE 6
DMA Controller
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