Altera cyclone V Technical Reference page 1179

16-28
DMA Channel Thread in Secure State
DMA Channel Thread in Secure State
When the
perform secure instruction fetches.
When a DMA channel thread in the secure state processes the following instructions:
•
DMAWFE
DMAC continues execution of the thread, regardless of the security state of the corresponding
in the
CR3
•
DMASEV
bit in the
INS
•
DMAWFP
point the DMAC continues execution of the thread, regardless of the security state of the
corresponding
•
DMALDP
is complete, regardless of the security state of the corresponding
•
DMAFLUSHP
resend its level status, regardless of the security state of the corresponding
When a DMA channel thread is in the secure state, it enables the DMAC to perform secure and
non-secure AXI accesses.
DMA Channel Thread in Non-Secure State
When the
only perform non-secure instruction fetches.
When a DMA channel thread in the non-secure state processes the following instructions:
- The DMAC uses the status of the corresponding
DMAWFE
for the event.
• If =0, then the event is in the secure state. The DMAC:
INS
• Executes an
• Sets the appropriate bit in the
• Sets the
• Moves the DMA channel to the Faulting completing state
• If =1, then the event is in the non-secure state. The DMAC halts execution of the thread and waits
INS
for the event to occur.
- The DMAC uses the status of the corresponding
DMASEV
the event.
• If =0, then the event-interrupt resource is in the secure state. The DMAC:
INS
• Executes an
• Sets the appropriate bit in the
• Sets the
• Moves the DMA channel to the Faulting completing state
• If =1, then the event-interrupt resource is in the non-secure state. The DMAC creates the event
INS
interrupt.
Altera Corporation
bit is 0, the DMA channel thread is programmed to operate in the secure state and to only
CNS
- The DMAC halts execution of the thread until the event occurs. When the event occurs, the
register.
- The DMAC creates the event interrupt, regardless of the security state of the corresponding
register.
CR3
- The DMAC halts execution of the thread until the peripheral signals a DMA request at which
bit in the
PNS CR4
and - The DMAC sends a message to the peripheral to communicate that data transfer
DMASTP
- The DMAC clears the state of the peripheral and sends a message to the peripheral to
bit is 1, the DMA channel thread is programmed to operate in the non-secure state and to
CNS
NOP
bit in the
ch_evnt_err
NOP
bit in the
ch_evnt_err
register.
INS
register corresponding to the DMA channel number
FSRC
register
FTRn
INS
register corresponding to the DMA channel number
FSRC
register
FTRn
bit in the register.
PNS CR4
bit in the
PNS
bit in the register, to control if it waits
CR3
bit in the register, to control if it creates
CR3
cv_5v4
2016.10.28
bit
INS
register.
CR4
DMA Controller
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