Altera cyclone V Technical Reference page 1175

16-24
Watchdog Abort
• A DMA channel thread attempts to execute
performs the store, the MFIFO buffer contains insufficient data to enable it to complete the store.
• A DMA channel thread in the Non-secure state executes
peripheral request interface that is set as secure. The
initialize the security state for a peripheral request interface.
• A DMA manager thread in the Non-secure state executes
channel thread.
• The DMAC receives an ERROR response on the AXI master interface when it performs an instruction
fetch.
• A thread executes an undefined instruction.
• A thread executes an instruction with an operand that is invalid for the configuration of the DMAC.
Note: When the DMAC signals a precise abort, the instruction that triggers the abort is not executed.
Instead, the DMAC executes a
The DMAC signals an imprecise abort under the following conditions:
• The DMAC receives an ERROR response on the AXI master interface when it performs a data load.
• The DMAC receives an ERROR response on the AXI master interface when it performs a data store.
• A DMA channel thread executes
required amount of data.
• A DMA channel thread executes
• A DMA channel thread locks up because of resource starvation, and this causes the internal watchdog
timer to time out.
Watchdog Abort
The DMAC can lock up if one or more DMA channel programs are running and the MFIFO buffer is too
small to satisfy the storage requirements of the DMA programs.
The DMAC contains logic to prevent it from remaining in a state where it is unable to complete a DMA
transfer.
The DMAC detects a lock up when all of the following conditions occur:
• Load queue is empty.
• Store queue is empty.
• All of the running channels are prevented from executing a
MFIFO buffer does not have sufficient free space or another channel owns the load-lock.
When the DMAC detects a lockup, it signals an interrupt and can also abort the contributing channels.
The DMAC behavior depends on the state of the
•
wd_irq_only
signal high.
•
wd_irq_only
Related Information
Resource Sharing Between DMA Channels
Altera Corporation
DMANOP
DMALD
DMAST
=0—The DMAC aborts all of the contributing DMA channels and sets the
=1—The DMAC sets the
but the DMAC calculates that when it eventually
DMAST
DMAWFP
boot_periph_ns
DMAGO
.
or , and the MFIFO buffer is too small to hold the
DMAST
but the thread has not executed sufficient
DMALD
bit in the
wd_irq_only
signal high.
irq_abort
on page 16-31
, , , or
DMALDP DMASTP DMAFLUSHP
memory-mapped control signals
to attempt to start a secure DMA
instructions.
DMALD
instruction either because the
register, if:
WD
irq_abort
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2016.10.28
for a
DMA Controller