Altera cyclone V Technical Reference page 1178

cv_5v4
2016.10.28
DMA Manager Thread in Secure State
If the bit is 0, the DMA manager thread operates in the secure state and performs only secure instruc‐
DNS
tion fetches. When a DMA manager thread in the secure state processes:
• —The DMAC uses the status of the
DMAGO
writing to the
• —The DMAC halts execution of the thread until the event occurs. When the event occurs, the
DMAWFE
DMAC continues execution of the thread, irrespective of the security state of the corresponding
bit.
• —The DMAC sets the corresponding bit in the
DMASEV
security state of the corresponding
DMA Manager Thread in Non-Secure State
If the bit is 1, the DMA manager thread operates in the non-secure state, and it only performs
DNS
non-secure instruction fetches. When a DMA manager thread in the non-secure state processes:
- The DMAC uses the status of the
DMAGO
• If = 0, then the DMAC does not start a DMA channel thread and instead it:
ns
• Executes an
• Sets the
• Sets the
• Moves the DMA manager to the Faulting state
• If = 1, then the DMAC starts a DMA channel thread in the non-secure state and programs the
ns
bit to be non-secure.
- The DMAC uses the status of the corresponding
DMAWFE
waits for the event.
• If = 0, then the event is in the secure state. The DMAC:
INS
• Executes an
• Sets the
• Sets the
• Moves the DMA manager to the Faulting state
• If = 1, then the event is in the non-secure state. The DMAC halts execution of the thread and waits
INS
for the event to occur.
- The DMAC uses the status of the corresponding
DMASEV
the event interrupt.
• If = 0, then the event-interrupt resource is in the secure state. The DMAC:
INS
• Executes a
• Sets the
• Sets the
• Moves the DMA manager to the Faulting state
• If = 1, then the event-interrupt resource is in the non-secure state. The DMAC creates the event
INS
interrupt.
DMA Controller
Send Feedback
bit for that channel.
CNS
INS
NOP
register
FSRD
bit in the
dmago_err FTRD
NOP
register
FSRD
bit in the
mgr_evnt_err
NOP
register
FSRD
bit in the
mgr_evnt_err
DMA Manager Thread in Secure State
bit, to set the security state of the DMA channel thread by
ns
INT_EVENT_RIS
bit.
bit to control if it starts a DMA channel thread.
ns
register
bit in the
INS
register
FTRD
bit in the
INS
register
FTRD
register, irrespective of the
register to control whether it
CR3
register to control if it creates
CR3
Altera Corporation
16-27
INS
CNS