Programmable Bandwidth; Phase Shift Implementation - Altera Cyclone IV Device Handbook

5–32

Programmable Bandwidth

The PLL bandwidth is the measure of the PLL's ability to track the input clock and its
associated jitter. PLLs of Cyclone IV devices provide advanced control of the PLL
bandwidth using the programmable characteristics of the PLL loop, including loop
filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines
the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.

Phase Shift Implementation

Phase shift is used to implement a robust solution for clock delays in Cyclone IV
devices. Phase shift is implemented with a combination of the VCO phase output and
the counter starting time. The VCO phase output and counter starting time are the
most accurate methods of inserting delays, because they are based only on counter
settings that are independent of process, voltage, and temperature.
You can phase shift the output clocks from the PLLs of Cyclone IV devices in one of
two ways:
Fine resolution using VCO phase taps
■
Coarse resolution using counter starting time
■
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution.
Equation 5–1
Equation 5–1. Fine Resolution Phase Shift
 fine
in which f
For example, if f

fine
depends on reference clock frequency and counter settings.
Coarse resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks.
shift.
Equation 5–2. Coarse Resolution Phase Shift
 coarse
C is the count value set for the counter delay time (this is the initial setting in the PLL
usage section of the compilation report in the Quartus II software). If the initial value
is 1, C – 1 = 0° phase shift.
Cyclone IV Device Handbook,
Volume 1
shows the minimum delay time that you can insert using this method.
T
1 N
VCO
-------------- --------------- - ------------------- -
= = =
8 8f 8Mf
VCO REF
is the input reference clock frequency.
REF
is 100 MHz, N = 1, and M = 8, then f
REF
= 156.25 ps. The PLL operating frequency defines this phase shift, a value that
 N
C 1 – C 1 –
------------ - ----------------------
= =
f Mf
V CO REF
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
= 800 MHz, and
VCO
Equation 5–2 shows the coarse phase
October 2012 Altera Corporation
Programmable Bandwidth