Chapter 5. Nios Ii Core Implementation Details - Altera Nios II User Manual

February 2014
NII51015-13.1.0
NII51015-13.1.0
This document describes all of the Nios
at the time of publishing. This document describes only implementation-specific
features of each processor core. All cores support the Nios II instruction set
architecture.
f
For more information regarding the Nios II instruction set architecture, refer to the
Instruction Set Reference
For common core information and details on a specific core, refer to the appropriate
section:
Table 5–1. Nios II Processor Cores (Part 1 of 3)
Feature
Objective
DMIPS/MHz
Performance Max. DMIPS
Max. f (2)
MAX
Area
Pipeline
External Address Space
Cache
Pipelined Memory Access
Instruction
Bus
Branch Prediction
Tightly-Coupled Memory
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Nios II Processor Reference Handbook
February 2014
5. Nios II Core Implementation Details
chapter of the Nios II Processor Reference Handbook.
Nios II/e
Minimal core size
(1) 0.15
(2) 31
200 MHz
< 700 LEs;
< 350 ALMs
1 stage
2 GB
–
–
–
–
®
II processor core implementations available
Core
Nios II/s
Small core size Fast execution speed
0.74 1.16
127 218
165 MHz 185 MHz
Without MMU or MPU:
< 1800 LEs;
< 900 ALMs
With MMU:
< 1400 LEs;
< 3000 LEs;
< 700 ALMs
< 1500 ALMs
With MPU:
< 2400 LEs;
< 1200 ALMs
5 stages 6 stages
2 GB without MMU
2 GB
4 GB with MMU
512 bytes to 64 KB 512 bytes to 64 KB
Yes Yes
Static Dynamic
Optional Optional
Nios II/f
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