Clocks And Resets - Altera Cyclone V Device Handbook

cv_54005
2013.12.30
Signal
RLAST
RVALID
RREADY

Clocks and Resets

FPGA-to-HPS Bridge
The master interface of the bridge in the HPS logic operates in the l3_main_clk clock domain. The slave
interface exposed to the FPGA fabric operates in the f2h_axi_clk fpga2hps_clkclock domain
provided by the user logic. The bridge provides clock crossing logic that allows the logic in the FPGA to
operate in any clock domain, asynchronous from the HPS.
The FPGA-to-HPS bridge has one reset signal, fpga2hps_bridge_rst_n. The reset manager drives
this signal to FPGA-to-HPS bridge on a cold or warm reset.
Related Information
• Clock Manager
For information about the l3_main_clk and l4_mp_clk clocks, refer to the Clock Manager chapter.
• Reset Manager
For more information about the reset manager, refer to the Reset Manager chapter.
• HPS Component Interfaces
For information about the f2h_axi_clk clock, refer to the HPS Component Interfaces chapter.
HPS-to-FPGA Bridge
The master interface into the FPGA fabric operates in the h2f_axi_clk clock domain. The h2f_axi_clk
clock is provided by user logic. The slave interface of the bridge in the HPS logic operates in the
l3_main_clk clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA
to operate in any clock domain, asynchronous from the HPS.
The HPS-to-FPGA bridge has one reset signal, hps2fpga_bridge_rst_n. The reset manager drives
this signal to HPS-to-FPGA bridge on a cold or warm reset.
Related Information
• Clock Manager
For information about the l3_main_clk and l4_mp_clk clocks, refer to the Clock Manager chapter.
• Reset Manager
For more information about the reset manager, refer to the Reset Manager chapter.
• HPS Component Interfaces
For information about the f2h_axi_clk clock, refer to the HPS Component Interfaces chapter.
HPS-FPGA AXI Bridges
Send Feedback
Width Direction
1 bit Input
1 bit Input
1 bit Output
on page 2-1
on page 3-1
on page 28-1
on page 2-1
on page 3-1
on page 28-1
Description
Read last data identifier
Read data channel valid
Read data channel ready
5-13
Clocks and Resets
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