Master Caching And Buffering Overrides - Altera Cyclone V Device Handbook

4-12

Master Caching and Buffering Overrides

Table 4-3: Memory Map Remap Bits
Bit Name
mpuzero
nonmpuzero
Reserved
hps2fpga
lwhp2fpga
Reserved
Note: L2 filter registers in the MPU subsystem, not the interconnect, allow the SDRAM to be remapped to
address 0 for the MPU.
Related Information
Cortex-A9 Microprocessor Unit Subsystem
For more information, refer to the Cortex-A9 Microprocessor Unit Subsystem chapter.
Master Caching and Buffering Overrides
Some of the masters of the interconnect do not have the ability to drive the caching and buffering signals of
their AXI and AHB interfaces. In order to ensure that these masters can perform transfers efficiently, the
registers are available from the system manager so that you can enable cacheable and bufferable transactions.
The following masters have their caching and buffering signals driven by the system manager:
• EMAC0 and EMAC1
• USB OTG 0 and USB OTG 1
• NAND flash
• SD/MMC
Altera Corporation
Bit Offset
0 When set to 0, the boot ROM maps to address 0x0 for the MPU
L3 master. When set to 1, the on-chip RAM maps to address 0x0
for the MPU L3 master. This bit has no effect on non-MPU
masters.
Note that regardless of this setting, the boot ROM also always maps
to address 0xffff_0000 and the on-chip RAM also always maps to
address 0xfffd_0000 for the MPU L3 master.
1 When set to 0, the SDRAM maps to address 0x0 for the non-MPU
L3 masters. When set to 1, the on-chip RAM maps to address 0x0
for the non-MPU masters. This bit has no effect on the MPU L3
master.
Note that regardless of this setting, the on-chip RAM also always
maps to address 0xfffd_0000 for the non-MPU L3 masters.
2 Must always be set to 0.
3 When set to 1, the HPS-to-FPGA bridge slave port is visible to the
L3 masters. When set to 0, accesses to the associated address range
return an AXI decode error to the master.
4 When set to 1, the lightweight HPS-to-FPGA bridge slave port is
visible to the L3 masters. When set to 0, accesses to the associated
address range return an AXI decode error to the master.
31:5 Must always be set to 0.
on page 6-1
Description
Send Feedback
cv_54004
2013.12.30
Interconnect