Fpga Interface Enables - Altera Cyclone V Device Handbook

14-6
L3 Interconnect
The preloader state register (initswstate) stores the magic number 0x49535756 written by the preloader
to indicate there is a valid preloader software image in the on-chip RAM.
There can be up to four preloader images stored in flash memory. The (initswlastld) register contains
the index of the preloader's last image that is loaded in the on-chip RAM.
The boot ROM software state register (bootromswstate) is a 32-bit general-purpose register reserved
for the boot ROM.
The following warmram related registers are used to configure the warm reset from on-chip RAM feature.
Table 14-1: The warmram Registers
Register
enable
datastart
length
execution
crc
All the registers in the above table must be written by software prior to the warm reset occurring.
The number of wait states applied to the boot ROM's read operation is determined by the wait state bit
(waitstate) of the ctrl register. After the boot process, software might require reading the code in the
boot ROM. If software has changed the clock frequency of the l3_main_clk after reset, an additional
wait state is necessary to access the boot ROM. Set the waitstate bit to add an additional wait state to
the read access of the boot ROM. The enable safe mode warm reset update bit controls whether the wait
state bit is updated during a warm reset.
L3 Interconnect
The System Manager provides remap bits to the L3 Interconnect. These bits can remap the Boot ROM and
the On-chip RAM.

FPGA Interface Enables

The system manager can enable or disable interfaces between the FPGA and HPS. The interfaces must be
disabled when not in use to avoid undefined behavior.
The global interface bit (intf) of the global disable register (gbl) disables all interfaces between the FPGA
and HPS.
Note: Ensure that all interfaces between the FPGA and HPS are inactive before disabling them.
Altera Corporation
Name
Enable Controls whether the boot ROM attempts to boot from the
contents of the on-chip RAM on a warm reset.
Data start Contains the byte offset of the warm boot CRC validation
region in the on-chip RAM. The offset must be word-
aligned to an integer multiple of four.
Length Contains the length in bytes of the region in the on-chip
RAM available for warm boot CRC validation.
Execution offset Contains the byte offset into the on-chip RAM that the
boot code jumps to if the CRC validation succeeds.
Expected CRC Contains the expected CRC of the region in the on-chip
RAM.
Purpose
System Manager
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2013.12.30