Altera cyclone V Technical Reference page 1183

16-32
Clocks and Resets
A channel releases ownership of the load-lock when any of the following occur:
• It executes a
• It reaches a barrier by executing
• It waits by executing
• It terminates normally, that is, it executes
• It aborts for any reason, including
The MFIFO buffer resource usage of a DMA channel program is measured in MFIFO buffer entries, and
rises and falls as the program proceeds. The MFIFO buffer resource requirement of a DMA channel
program is described using a static requirement and a dynamic requirement which are affected by the
load-lock mechanism.
The static requirement is defined to be the maximum number of MFIFO buffer entries that a channel is
currently using before that channel does one of the following:
• Executes a WFP or WFE instruction
• Claims ownership of the load-lock.
The dynamic requirement is defined to be the difference between the static requirement and the maximum
number of MFIFO buffer entries that a channel program uses at any time during its
To calculate the total MFIFO buffer requirement, add the largest dynamic requirement to the sum of all
the static requirements.
To avoid DMAC lockup, the total MFIFO buffer requirement of the set of channel programs must be equal
to or less than 512, the MFIFO buffer depth.
Related Information
Watchdog Abort
•
MFIFO Buffer Usage Overview
•
Clocks and Resets
Clock
The DMA controller operates on the
Related Information
Clock Manager
Resets
The DMA controller has nine reset signals. The reset manager drives the
controller on a cold or warm reset. The reset manager drives the
reset the eight FPGA PRIs.
Table 16-4: Reset inputs to the DMA controller
aresetn
dma_fpga_if_rst_n[7:0]
Altera Corporation
, , or
DMAST DMASTP DMASTZ
DMARMB
or
DMAWFP DMAWFE
DMAKILL
on page 16-24
on page 16-52
l4_main_clk
on page 2-1
Reset Signal
or
DMAWMB
DMAEND
input.
dma_fpga_if_rst_n[7:0]
Resets DMA controller
Resets the eight FPGA peripheral request interfaces
signal to the DMA
aresetn
signals to
Description
DMA Controller
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cv_5v4
2016.10.28