Altera cyclone V Technical Reference page 1258

Hard processor system
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cv_5v4
2016.10.28
Bit
25
Layer 4 Filter Match
When set, this bit indicates that the received frame matches one of the enabled Layer 4 Port
Number fields. This status is given only when one of the following conditions is true:
• Layer 3 fields are not enabled and all enabled Layer 4 fields match.
• All enabled Layer 3 and Layer 4 filter fields match.
When more than one filter matches, this bit gives the layer 4 filter status of filter indicated by
Bits [27:26].
24
Layer 3 Filter Match
When set, this bit indicates that the received frame matches one of the enabled Layer 3 IP
Address fields.
This status is given only when one of the following conditions is true:
• All enabled Layer 3 fields match and all enabled Layer 4 fields are bypassed.
• All enabled filter fields match.
When more than one filter matches, this bit gives the layer 3 filter status of the filter indicated
by Bits [27:26].
23:15
Reserved
14
Timestamp Dropped
When set, this bit indicates that the timestamp was captured for this frame but got dropped in
the MTL RX FIFO buffer because of overflow.
13
PTP Version
When set, this bit indicates that the received PTP message has the IEEE 1588 version 2 format.
When clear, it has the version 1 format.
12
PTP Frame Type
When set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit is
not set and the message type is non-zero, it indicates that the PTP message is sent over
UDP-IPv4 or UDP-IPv6. The information about IPv4 or IPv6 can be obtained from Bits 6 and
7.
Ethernet Media Access Controller
Send Feedback
Receive Descriptor Field 4 (RDES4)
Description
17-43
Altera Corporation

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