Altera cyclone V Technical Reference page 1198

cv_5v4
2016.10.28
where:
If S is present, the assembler sets
[S]
request_type
•
request_type
• The DMAC performs a
tion length is one. The DMAC ignores the v value of the dst_burst_len field in the channel control
registers.
•
request_type
• The DMAC performs a
tion. No state change occurs.
If B is present, the assembler sets
[B]
request_type
•
request_type
• The DMAC performs a
tion. No state change occurs.
•
request_type
• The DMAC performs a
• If you do not specify the S or B operand, the assembler sets
executes a DMA store.
Note: The DMAC sets the value of the
Operation
You can only use this instruction in a DMA channel thread. If you specify the S or B operand, execution of
the instruction is conditional on the state of the
The DMAC only commences the burst when the MFIFO buffer contains all of the data necessary to
complete the burst transfer.
Related Information
DMAWFP
DMASTP<S | B>
Store and notify Peripheral instructs the DMAC to transfer data from the FIFO buffer to the location that
the destination address registers specifies, using AXI transactions that the DA register and channel control
registers specify. It uses the DMA channel number to access the appropriate location in the FIFO buffer.
After the DMA store is complete, and the DMAC has received a buffered write response, it issues an
acknowledgement to the peripheral that the data transfer is complete. If the
control registers is set to incrementing, the DMAC updates the destination address registers after it
executes
DMASTP<S|B>
Figure 16-23: DMASTP<S|B> Instruction Encoding
DMA Controller
Send Feedback
flag:
= Single
instruction and it sets
DMAST
= Burst
instruction. The DMAC increments the channel PC to the next instruc‐
DMANOP
flag:
= Single
instruction. The DMAC increments the channel PC to the next instruc‐
DMANOP
= Burst
.
DMAST
on page 16-49
.
15 11
periph[4:0]
to 0 and to 1. The instruction is conditional on the state of the
bs x
awlen[3:0]
to 1 and to 1. The instruction is conditional on the state of the
bs x
flag when it executes a
request_type
request_type
10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0
DMASTP<S | B>
=0x0 so that the AXI write transac‐
to 0 and to 0, and the DMAC always
bs x
instruction.
DMAWFP
flag matching that of the instruction.
bit in the channel
dst_inc
1 0 bs 1
16-47
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