Altera cyclone V Technical Reference page 1252

cv_5v4
2016.10.28
Receive Descriptor Field 0 (RDES0)
Table 17-11: Receive Descriptor Field 0 (RDES0)
31
30
29:16
15
Ethernet Media Access Controller
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Bit
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA
of the EMAC. When this bit is cleared, this bit indicates that the
descriptor is owned by the Host. The DMA clears this bit either
when it completes the frame reception or when the buffers that are
associated with this descriptor are full.
AFM: Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the
MAC.
FL: Frame Length
These bits indicate the byte length of the received frame that was
transferred to host memory (including CRC)​. This field is valid
when Last Descriptor (RDES0[8]) is set and either the Descriptor
Error (RDES0[14]) or Overflow Error bits are cleared. The frame
length also includes the two bytes appended to the Ethernet frame
when IP checksum calculation (Type 1) is enabled and the received
frame is not a MAC control frame.
This field is valid when Last Descriptor (RDES0[8]) is set. When the
Last Descriptor and Error Summary bits are not set, this field
indicates the accumulated number of bytes that have been
transferred for the current frame.
ES: Error Summary
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header or Payload Error (Receive Descriptor
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
†
Field 4 (RDES4))
Receive Descriptor Field 0 (RDES0)
Description
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17-37
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