Altera cyclone V Technical Reference page 1188

cv_5v4
2016.10.28
Assembler syntax
DMAADNH <address_register>
where:
<address_register>
register and sets
SAR SARn
register and sets
DAR DARn
-
<16 bit immediate>
Note: You should specify the 16-bit immediate as the number that is to be represented in the instruction
encoding. For example,
current value of the Destination Address register, effectively subtracting 16 from the
Operation
You can only use this instruction in a DMA channel thread.
DMAEND
End signals to the DMAC that the DMA sequence is complete. After all DMA transfers are complete for
the DMA channel, the DMAC moves the channel to the Stopped state. It also flushes data from the MFIFO
buffer and invalidates all cache entries for the thread.
Figure 16-10: DMAEND Instruction Encoding
Assembler syntax
DMAEND
Operation
You can use the instruction with the DMA manager thread and the DMA channel thread.
DMAFLUSHP
Flush Peripheral clears the state in the DMAC that describes the contents of the peripheral and sends a
message to the peripheral to resend its level status.
Figure 16-11: DMAFLUSHP Instruction Encoding
DMA Controller
Send Feedback
, -
<16 bit immediate>
Selects the address register to use. It must be either:
to 0
ra
to 1
ra
The immediate value to be added to the
, 0xFFF0 causes the value 0xFFFFFFF0 to be added to the
DMAADNH DAR
7 6 5 4 3 2 1 0
0 0 0
11 10 9
15
periph[4:0] 0 0 0
<address_register>
0 0 0 0 0
8
7 6 5 4 3 2 1 0
0 0 1 1 0 1 0 1
16-37
DMAEND
.
.
DAR
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