Altera cyclone V Technical Reference page 1233

17-18
Host Bus Burst Access
Note: You can select a descriptor structure during RTL configuration. The control bits in the descriptor
structure are assigned so that the application can use an 8 KB buffer. All descriptions refer to the
default descriptor structure.
Related Information
Ethernet MAC Address Map and Register Definitions
Information about control and status registers
Host Bus Burst Access
The DMA attempts to execute fixed-length burst transfers on the master interface if configured to do so
through the
limited by the
are always accessed in the maximum possible (limited by packet burst length (PBL) or 16 * 8/bus width)
burst size for the 16- bytes to be read.
The transmit DMA initiates a data transfer only when the MTL transmit FIFO has sufficient space to
accommodate the configured burst or the number of bytes remaining in the frame (when it is less than the
configured burst length). The DMA indicates the start address and the number of transfers required to the
master interface. When the interface is configured for fixed-length burst, it transfers data using the best
combination of INCR4, 8, or 16 and SINGLE transactions. When not configured for fixed-length burst, it
transfers data using INCR (undefined length) and SINGLE transactions.
The receive DMA initiates a data transfer only when sufficient data to accommodate the configured burst
is available in MTL receive FIFO buffer or when the end of frame (when it is less than the configured burst
length) is detected in the receive FIFO buffer. The DMA indicates the start address and the number of
transfers required to the master interface. When the interface is configured for fixed-length burst, it
transfers data using the best combination of INCR4, 8, or 16 and SINGLE transactions. If the end-of-
frame is reached before the fixed burst ends on the interface, then dummy transfers are performed in order
to complete the fixed burst. If the
INCR (undefined length) and SINGLE transactions.
When the interface is configured for address aligned words, both DMA engines ensure that the first burst
transfer initiated is less than or equal to the size of the configured packet burst length. Thus, all subsequent
beats start at an address that is aligned to the configured packet burst length. The DMA can only align the
address for beats up to size 16 (for PBL > 16), because the interface does not support more than INCR16.
Host Data Buffer Alignment
The transmit and receive data buffers do not have any restrictions on start address alignment. For example,
in systems with 32-bit memory, the start address for the buffers can be aligned to any of the four bytes.
However, the DMA always initiates transfers with address aligned to the bus width with dummy data for
the byte lanes not required. This typically happens during the transfer of the beginning or end of an
Ethernet frame. The software driver should discard the dummy bytes based on the start address of the
buffer and size of the frame.
Example: Buffer Read
If the transmit buffer address is 0x00000FF2, and 15 bytes must be transferred, then the DMA reads five
full words from address 0x00000FF0, but when transferring data to the MTL transmit FIFO buffer, the
extra bytes (the first two bytes) are dropped or ignored. Similarly, the last three bytes of the last transfer are
also ignored. The DMA always ensures it transfers data in 32-bit increments to the MTL transmit FIFO
buffer, unless it is the end-of-frame.
Altera Corporation
bit of Register 0 (
FB Bus Mode Register
field (Bits [13:8]) Register 0 (Bus Mode Register). The receive and transmit descriptors
PBL
FB
†
on page 17-72
). The maximum burst length is indicated and
bit of Register 0 (Bus Mode Register) is clear, it transfers data using
2016.10.28
Ethernet Media Access Controller
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