Altera cyclone V Technical Reference page 1235

17-20
TX DMA Operation: Default (Non-OSF) Mode
5. The DMA fetches the transmit data from the Host memory and transfers the data to the MTL for
transmission.
6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes the
intermediate descriptor and fetches the next descriptor. Repeat
of-Ethernet-frame data is transferred to the MTL.
7. When frame transmission is complete, if IEEE 1588 timestamping was enabled for the frame (as
indicated in the transmit status) the timestamp value obtained from MTL is written to the transmit
descriptor (TDES2 and TDES3) that contains the end-of-frame buffer. The status information is then
written to this transmit descriptor (TDES0). Because the Own bit is cleared during this step, the Host
now owns this descriptor. If timestamping was not enabled for this frame, the DMA does not alter the
contents of TDES2 and TDES3.
8. Bit 0 (Transmit Interrupt) of Register 5 (Status Register) is set after completing transmission of a frame
that has Interrupt on Completion (TDES1[31]) set in its Last descriptor. The DMA engine then returns
step
to
9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to
receives a Transmit Poll demand and the Underflow Interrupt Status bit is cleared.
Altera Corporation
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3.
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step 3, step 4, and step 5
step
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Ethernet Media Access Controller
cv_5v4
2016.10.28
until the end-
3) when it
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