Altera cyclone V Technical Reference page 1224

cv_5v4
2016.10.28
emac_phy_txd_o[7:0]
emac_phy_txen_o
emac_phy_txer_o
emac_rst_clk_tx_n_o
emac_clk_rx_i
Ethernet Media Access Controller
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Signal Name
PHY Transmit Data
PHY Transmit Data
Enable
PHY Transmit Error
Transmit Clock Reset
output
Receive Clock
FPGA EMAC I/O Signals
In/Out Width
Out 8 These are a group of eight
transmit data signals driven by
the EMAC.
All eight bits provide the GMII
transmit data byte. For the lower
speed MII operation, only
bits[3:0] are used. The validity of
the data is qualified with
phy_txen_o
Synchronous to
Out 1 This signal is driven by the
EMAC and is used in GMII
mode. When driven high, this
signal indicates that valid data is
being transmitted on the
clk_tx_o
Out 1 This signal is driven by the
EMAC and when high, indicates
a transmit error or carrier
extension on the
is also used to signal low power
states in Energy Efficient
Ethernet operation.
Out 1 Transmit clock reset output to
the FPGA fabric, which is the
internal synchronized reset to
clk_tx_int
EMAC. May be used by logic
implemented in the FPGA fabric
as desired.
The reset pulse width of the
rst_clk_tx_n_o
transmit clock cycles.
Receive clock from external PHY.
In 1
For GMII, the clock frequency is
125 MHz. For MII, the receive
clock is 25 MHz for 100 Mbps
and 2.5 MHz for 10 Mbps.
17-9
Description
and .
phy_txer_o
.
phy_txclk_o
bus.
bus. It
phy_txd
output from the
signal is three
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