Altera cyclone V Technical Reference page 1246

cv_5v4
2016.10.28
Figure 17-11: Transmit Descriptor Fetch (Read) Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
O
TDES0 W Ctrl [30:26]
N
RES
TDES1
[31:29]
T E D 2 S
T E D 3 S
Table 17-5: Transmit Descriptor Word 0 (TDES0)
Bit
31 OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is cleared,
it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it
completes the frame transmission or when the buffers allocated in the descriptor are read
completely. The ownership bit of the frame's first descriptor must be set after all subsequent
descriptors belonging to the same frame have been set to avoid a possible race condition
between fetching a descriptor and the driver setting an ownership bit.
30 IC: Interrupt on Completion
When set, this bit enables the Transmit Interrupt (Register 5[0]) to be set after the present
frame has been transmitted.
29 LS: Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame. When this bit
is set, the TBS1 or TBS2 field in TDES1 should have a non-zero value.
28 FS: First Segment
When set, this bit indicates that the buffer contains the first segment of a frame.
27 DC: Disable CRC
When this bit is set, the MAC does not append a CRC to the end of the transmitted frame. This
bit is valid only when the first segment (TDES0[28]) is set.
Ethernet Media Access Controller
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T
T
Ctrl [24:18]
S
E
Buffer 2 Byte Count [28:16]
u B
u B r e f f A 2 r d d s s e 3 [
†
Reserved for Status [17:7]
RES
r e f f A 1 r d d s s e 1 3 [ ] 0 :
0 : 1 o ] N r x e D t s e i r c o t p A r r d d
Description
†
Transmit Descriptor
9 8 7 6 5 4
SLOT
Number [6:3]
Buffer 1 Byte Count [12:0]
s s e 1 3 [ ] 0 :
†
†
†
Altera Corporation
17-31
3 2 1 0
Reserved
for
Status
[2:0]