Altera cyclone V Technical Reference page 1251

17-36
Receive Descriptor
Table 17-10: Transmit Descriptor 7 (TDES7)
Bit
31:0 TTSH: Transmit Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for
the corresponding receive frame. This field has the timestamp only if the Last Segment bit (LS)
in the descriptor is set and Timestamp status (TTSS) bit is set.
Receive Descriptor
The receive descriptor can have 32 bytes of descriptor data (8 DWORDs) when advanced timestamp or
IPC Full Offload feature is selected. When either of these features is enabled, software should set bit 7 of
Register 0 (Bus Mode Register) so that the DMA operates with extended descriptor size. When this control
bit is clear, the RDES0[0] is always cleared and the RDES4-RDES7 descriptor space is not valid.
Note: Only enhanced descriptor formats (4 or 8 DWORDS) are supported.
Figure 17-12: Receive Enhanced Descriptor Fields Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
O
RDES0 W
N
C
T RE S
RDES1
R [30:29]
L
R E D 2 S
R E D 3 S
R E D 4 S
R E D 5 S
R E D 6 S
R E D 7 S
Altera Corporation
Buffer 2 Byte Count [28:16]
u B
u B r e f f A 2 r d d s s e
Receive Timestamp Low [31:0]
Receive Timestamp High[31:0]
Description
†
Status [30:0]
R
Ctrl
E
[15:14]
S
r e f f A 1 r d d s s e 1 3 [ ] 0 :
3 [ 0 : 1 o ] N r x e D t s e i r c ptor A r d d
E e t x d n d e a t s s u t 1 3 [ ] 0 :
R s e v r e d e
†
9 8 7 6 5 4
Buffer 1 Byte Count [12:0]
s s e 1 3 [ ] 0 :
Ethernet Media Access Controller
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2016.10.28
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