Altera cyclone V Technical Reference page 1191

16-40
DMALD[S | B]
DMALD[S | B]
Load instructs the DMAC to perform a DMA load, using AXI transactions that the source address
registers and channel control registers specify. It places the read data into the MFIFO buffer and tags it
with the corresponding channel number.
are conditional on the state of the
set to incrementing, the DMAC updates the source address registers after it executes
Note: The DMAC sets the value of
Figure 16-14: DMALD[S|B] Instruction Encoding
Assembler syntax
DMALD[S|B]
where:
If S is present, the assembler sets
[S]
request_type
•
request_type
The DMAC performs a
length is one. The DMAC ignores the value of the src_burst_len field in the channel control registers.
•
request_type
The DMAC performs a
tion. No state change occurs.
If B is present, the assembler sets
[B]
request_type
•
request_type
The DMAC performs a
tion. No state change occurs.
•
request_type
The DMAC performs a
If you do not specify the S or B operand, the assembler sets
executes a DMA load.
Operation
You can only use this instruction in a DMA channel thread. If you specify the S or B operand, execution of
the instruction is conditional on the state of
DMALDP<S | B>
Load and notify Peripheral instructs the DMAC to perform a DMA load, using AXI transactions that
source address registers and channel control registers specify. It places the read data into a FIFO buffer
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request_type
request_type
bs
flag:
= Single
instruction and it sets
DMALD
= Burst
instruction. The DMAC increments the channel PC to the next instruc‐
DMANOP
bs
flag:
= Single
instruction. The DMAC increments the channel PC to the next instruc‐
DMANOP
= Burst
.
DMALD
is an unconditional instruction but
DMALD
flag. If the
src_inc
when it executes a
7 6 5 4 3 2 1 0
0 0 0 0 0 1 bs x
to 0 and to 1. The instruction is conditional on the state of the
x
arlen[3:0]
to 1 and to 1. The instruction is conditional on the state of the
x
to 0 and
bs
matching that of the instruction.
request_type
DMALDS
bit in the channel control registers is
DMALD[S|B]
instruction.
DMAWFP
=0x0 so that the AXI read transaction
to 0, and the DMAC always
x
cv_5v4
2016.10.28
and
DMALDB
.
DMA Controller
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