Altera cyclone V Technical Reference page 1181

16-30
Fixed Unaligned Bursts
Fixed Unaligned Bursts
The DMAC does not support fixed unaligned bursts. The DMAC treats the following conditions as
programming errors:
• Unaligned read
•
src_inc
• The
field contains.
• Unaligned write
•
dst_inc
• The
field contains.
Endian Swap Size Restrictions
If you program the
endian swap, then you must set the corresponding
contain an address that is aligned to the size that the
any
DMALD
Note: If you update any of
tion, then you must ensure that the
that the
tions.
If you program the
src_burst_size
endian_swap_size
address, you must program the
the value that the
If you program the
the register so that
CCRn
example, if
program
dst_burst_len
Updating DMA Channel Control Registers During a DMA Cycle
Prior to the DMAC executing a sequence of
the register,
CCRn
performs when it transfers the data from the source address to the destination address.
You can update these registers during a DMA cycle, but if you change certain register fields, then the
DMAC may discard data. The following sections describe the register fields that could have a detrimental
impact on a data transfer.
Updates that affect the destination address
If you use a
cycle, then there may be a discontinuity in the destination data stream.
Altera Corporation
field is 0 in the
CCRn
register contains an address that is not aligned to the size of data that the
SARn
field is 0 in the
CCRn
register contains an address that is not aligned to the size of data that the
DARn
endian_swap_size
or instructions.
DMAST
endian_swap_size
endian_swap_size
field in the
src_inc
field to select a burst size that is greater than or equal to the value that the
field specifies. Similarly, if you program the
dst_burst_size
endian_swap_size
field in the
dst_inc
dst_burst_len
= 2, 32-bit, and
endian_swap_size
= 1, 3, 5, ..., 15, that is 2, 4, 6, ..., 16 transfers.
register, and
SARn
instruction to update the
DMAMOV
register.
register.
field in the register, to enable a DMA channel to perform an
CCRn
register and the corresponding
SAR
endian_swap_size
, , or
SARn DARn
and registers contain an address aligned to the size
SARn DARn
field specifies before executing any additional
register to use a fixed address, you must program the
CCR
field to select a burst size that is greater than or equal to
field specifies.
register to use an incrementing address, you must program
CCRn
times
dst_burst_size
dst_burst_size
and
DMALD DMAST
register control the data byte lane manipulation that the DMAC
DARn
register or
DARn
field specifies before executing
, for example, using a
DMAADDH SAR
DMALD
field to select a fixed destination
dst_inc
is a multiple of
endian_swap_size
= 1, 2 bytes per beat, then you can
instructions, the values you program in to
register part way through a DMA
CCRn
cv_5v4
2016.10.28
src_burst_size
dst_burst_size
register to
DARn
instruc‐
or instruc‐
DMAST
. For
DMA Controller
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