Altera cyclone V Technical Reference page 1192

cv_5v4
2016.10.28
that is tagged with the corresponding channel number and after it receives the last data item, it sends an
acknowledgement to the peripheral that the data transfer is complete. If the
control registers is set to incrementing, the DMAC updates source address registers after it executes
DMALDP<S|B>
Figure 16-15: DMALDP<S|B> Instruction Encoding
Assembler syntax
DMALDP<S|B> <peripheral>
where:
When S is present, the assembler sets
<S>
request_type
•
request_type
The DMAC performs a
length is one. The DMAC ignores the value of the src_burst_len field in the channel control registers.
•
request_type
The DMAC performs a
When B is present, the assembler sets
<B>
request_type
•
request_type
The DMAC performs a
•
request_type
The DMAC performs a load using a burst DMA transfer.
<peripheral>
Note: The DMAC sets the value of the
Operation
You can only use this instruction in a DMA channel thread. Execution of the instruction is conditional on
the state of the
DMALP
Loop instructs the DMAC to load an 8-bit value into the loop counter register you specify.
This instruction indicates the start of a section of instructions, and you set the end of the section using the
instruction. The DMAC repeats the set of instructions that you insert between
DMALPEND
until the value in the loop counter register reaches zero.
DMALPEND
DMA Controller
Send Feedback
.
15
periph[4:0]
flag:
= Single
instruction and it sets
DMALDP
= Burst
.
DMANOP
flag:
= Single
.
DMANOP
= Burst
5-bit immediate, value 0-31.
flag matching that of the instruction.
request_type
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0
to 0. The instruction is conditional on the state of the
bs
arlen[3:0]
to 1. The instruction is conditional on the state of the
bs
flag when it executes a
request_type
DMALP
bit in the channel
src_inc
1 bs 1
=0x0 so that the AXI read transaction
instruction.
DMAWFP
DMALP
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16-41
and