Altera cyclone V Technical Reference page 1240

cv_5v4
2016.10.28
Mode Register)). The DMA closes the current descriptor (clears the Own bit) and marks it as
intermediate by clearing the Last Segment (LS) bit in the RDES0 value (marks it as Last Descriptor if
flushing is not disabled), then proceeds to
current frame transfer is not complete, the DMA closes the current descriptor as intermediate and
reverts to
7. If IEEE 1588 timestamping is enabled, the DMA writes the timestamp (if available) to the current
descriptor's RDES2 and RDES3. It then takes the receive frame's status from the MTL and writes the
status word to the current descriptor's RDES0, with the Own bit cleared and the Last Segment bit set.
8. The receive engine checks the latest descriptor's Own bit. If the host owns the descriptor (Own bit is 0),
the Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set and the DMA receive engine
enters the Suspended state (Step 9). If the DMA owns the descriptor, the engine returns to
awaits the next frame.
9. Before the receive engine enters the Suspend state, partial frames are flushed from the receive FIFO
buffer. You can control flushing using Bit 24 of Register 6 (Operation Mode Register).
10.The receive DMA exits the Suspend state when a Receive Poll demand is given or the start of next
frame is available from the MTL's receive FIFO buffer. The engine proceeds to
next descriptor.
Ethernet Media Access Controller
Send Feedback
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step 4.
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step 8. If the DMA does own the next descriptor but the
17-25
Reception
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step 4
and
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step 2
and refetches the
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