Altera cyclone V Technical Reference page 1243

17-28
Error Response to DMA
within a group are cleared, the corresponding summary bit is cleared. When both the summary bits are
cleared, the
interrupt, then any of the
Figure 17-9: Summary Interrupt (sbd_intr_o) Generation
Note: Register 5 (Status Register) is the interrupt status register. The interrupt pin (
asserted because of any event in this status register only if the corresponding interrupt enable bit is
set in Register 7 (Interrupt Enable Register).
Interrupts are not queued, and if the interrupt event occurs before the driver has responded to it, no
additional interrupts are generated. For example, Bit 6 (Receive Interrupt) of Register 5 (Status Register)
indicates that one or more frames were transferred to the Host buffer. The driver must scan all descriptors,
from the last recorded position to the first one owned by the DMA.
An interrupt is generated only once for multiple, simultaneous events. The driver must scan Register 5
(Status Register) for the cause of the interrupt. After the driver has cleared the appropriate bit in Register 5
(Status Register), the interrupt is not generated again until a new interrupting event occurs. For example,
the controller sets Bit 6 (Receive Interrupt) of Register 5 (Status Register) and the driver begins reading
Register 5 (Status Register). Next, the interrupt indicated by Bit 7 (Receive Buffer Unavailable) of Register
5 (Status Register) occurs. The driver clears the receive interrupt (bit 6). However, the
not deasserted, because of the active or pending Receive Buffer Unavailable interrupt.
Bits 7:0 (
riwt
of the receive interrupt. When this Interrupt timer is programmed with a non-zero value, it gets activated
as soon as the RX DMA completes a transfer of a received frame to system memory without asserting the
receive Interrupt because it is not enabled in the corresponding Receive Descriptor (RDES1[31]). When
this timer runs out as per the programmed value, the
corresponding
out, when a frame is transferred to memory, and the receive interrupt is triggered if it is enabled.
Related Information
Receive Descriptor
Error Response to DMA
If the slave replies with an error response to any data transfer initiated by a DMA channel, that DMA stops
all operations and updates the error bits and the Fatal Bus Error bit in the Register 5 (Status Register). The
(60) Signals NIS and AIS are registered.
Altera Corporation
interrupt signal is deasserted. If the MAC is the cause for assertion of the
sbd_intr_o
, ,
GLI GMI TTI
TI
TIE
ERI
ERE
TPS
TSE
FBI
FBE
field)​ of Register 9 (Receive Interrupt Watchdog Timer Register) provide for flexible control
is enabled in Register 7 (Interrupt Enable Register). This timer is disabled before it runs
AIE
on page 17-36
, or bits of Register 5 (Status Register) are set to 1.
GLPII
(60)
TTI
GMI
GLI
NIS GLPII/GTMSI
NIE
AIS
AIE
†
bit is set and the interrupt is asserted if the
AIS
2016.10.28
sbd_intr_o
) is
sbd_intr_o
signal is
sbd_intr_o
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