Altera cyclone V Technical Reference page 1228

cv_5v4
2016.10.28
Table 17-4: EMAC to FPGA IEEE 1588 Timestamp Interface Signals
f2h_emac_ptp_ref_clk
ptp_pps_o
ptp_aux_ts_trig_i
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Signal Name
Timestamp PTP
Clock reference from
the FPGA
Pulse Per Second
Output
Auxiliary Timestamp
Trigger
Timestamp Interface
In/Out Width
In 1 Used as PTP Clock reference
for each EMAC when the
FPGA has implemented
Timestamp capture interface.
Common for both EMACs.
Out 1 This signal is asserted based on
the PPS mode selected in the
Register 459 (PPS Control
Register). Otherwise, this pulse
signal is asserted every time the
seconds counter is
incremented. This signal is
synchronous to
ptp_ref_clk
sampled if the FPGA clock is
used as timestamp reference.
In 1 This signal is asserted to take
an auxiliary snapshot of the
time.
The rising edge of this internal
signal is used to trigger the
auxiliary snapshot. The signal is
synchronized internally with
clk_ptp_ref_i
in an additional delay of 3
cycles. This input is asynchro‐
nous input and its assertion
period must be greater than 2
PTP active clocks to be
sampled.
17-13
Description
f2h_emac_
and may only be
which results
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