Altera cyclone V Technical Reference page 1209

Hard processor system

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Aligned Burst Size Unaligned MFIFO Buffer

DMALD ; shown as e in the figure below

DMAMOV CCR, SB1 SS32 DB4 DS64

DMALD ; shown as f in the figure below

DMAST ; shown as g in the figure below

Figure 16-33: Unaligned to Aligned with Excess Initial Load

After the first

satisfy the final

MFIFO buffer entry that the DMAC has already allocated to this channel.

This example has a static requirement of one MFIFO buffer entry and a dynamic requirement of four

MFIFO buffer entries.

Related Information

Unaligned Source Address to Aligned Destination Address

Aligned Burst Size Unaligned MFIFO Buffer

In this program, the destination address, which is narrower than the MFIFO buffer width, aligns with the

burst size, but does not align with the MFIFO buffer width.

DMAMOV CCR, SB4 SS32 DB4 DS32

DMAMOV SAR, 0x1000

Altera Corporation

instruction loads five bursts of data to enable the DMAC to execute the first

, the subsequent

reads from address 0x1028. After the loop, the final two

shown as f does not increase the MFIFO buffer usage because it loads four bytes into an

s are not aligned to the source burst size, for example the

s read the data required to

a a a a a a a a

c c c a a a a

c c c c c c c c

e e e e e e e e

f f f f e e e e

on page 16-56

DMA Controller

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