Altera cyclone V Technical Reference page 1187

16-36
DMAADDH
DMAADDH
Add Halfword adds an immediate 16-bit value to the
thread. This enables the DMAC to support two-dimensional DMA operations.
Note: The immediate unsigned 16-bit value is zero-extended before the DMAC adds it to the address,
using 32-bit addition. The DMAC discards the carry bit so that addresses wrap from 0xFFFFFFFF
to 0x00000000.
Figure 16-8: DMAADDH Instruction Encoding
Assembler syntax
DMAADDH <address_register>, <16-bit bit immediate>
where:
<address_register>
•
SAR SARn
•
DAR DARn
-
<16 bit immediate>
Operation
You can only use this instruction in a DMA channel thread.
DMAADNH
Add Negative Halfword adds an immediate negative 16-bit value to the
the DMA channel thread. This enables the DMAC to support two-dimensional DMA operations, or
reading or writing an area of memory in a different order to naturally incrementing addresses.
Note: The immediate unsigned 16-bit value is one-extended to 32 bits, to create a value that is the two's
complement representation of a negative number between -65536 and -1, before the DMAC adds it
to the address using 32-bit addition. The DMAC discards the carry bit so that addresses wrap from
0xFFFFFFFF to 0x00000000. The net effect is to subtract between 65536 and 1 from the current
value in the source or destination address register.
Figure 16-9: DMAADNH Encoding
Altera Corporation
23 16
imm[15:8]
Selects the address register to use. It must be either:
register and sets to 0
ra
register and sets to 1
ra
The immediate value to be added to the
23 16
imm[15:8]
register or
SARn
15 8
imm[7:0]
<address_register>
15 8 7 6 5 4 3 2 1 0
imm[7:0] 0 0
register, for the DMA channel
DARn
7 6 5 4 3 2 1 0
0 1 0 1 0 1 ra 0
.
register or
SARn DARn
0 1 1 1 ra 0
cv_5v4
2016.10.28
register, for
DMA Controller
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