Altera cyclone V Technical Reference page 1222

cv_5v4
2016.10.28
Table 17-1: HPS EMAC I/O Signals
phy_txclk_o
phy_txd_o
phy_txen_o
phy_clk_rx_i
phy_rxd_i
Ethernet Media Access Controller
Send Feedback
EMAC Port
Transmit Clock
PHY Transmit Data
PHY Transmit Data
Enable
Receive Clock
PHY Receive Data
HPS EMAC I/O Signals
In/Out Width
Out 1 This signal provides the transmit
clock for RGMII (125/25/2.5
MHz in 1G/100M/10Mbps).
All PHY transmit signals
generated by the EMAC are
synchronous to this clock.
Out 8 This group of eight transmit data
signals is driven by the MAC.
Bits [3:0] provide the RGMII
transmit data. Unused bits in the
RGMII interface configuration
are tied low. In RGMII mode, the
data bus carries transmit data at
double rate and are sampled on
both the rising and falling edges
of the transmit clock. The
validity of the data is qualified
with
phy_txen_o
Out 1 This signal is driven by the
EMAC component, and in
RGMII mode acts as the control
signal (
transmit data, and is driven on
both edges of the transmit clock,
phy_txclk_o
In 1 In RGMII mode, this clock
frequency is 125/25/2.5 MHz in
1 G/100 M/10 Mbps modes. It is
provided by the external PHY.
All PHY signals received by the
EMAC are synchronous to this
clock.
These eight data signals are
In 8
received from the PHY and carry
receive data at double rate with
bits[3:0] valid on the rising edge
of
phy_rxclk_i
valid on the falling edge of
rxclk_i
is qualified with
17-7
Description
.
) for the
rgmii_tctl
.
, and bits[7:4]
phy_
. The validity of the data
.
phy_rxdv_i
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