Altera cyclone V Technical Reference page 1234

cv_5v4
2016.10.28
Example: Buffer Write
If the receive buffer address is 0x00000FF2 and 16 bytes of a received frame must be transferred, then the
DMA writes 3 full words from address 0x00000FF0. But the first two bytes of first transfer and the last two
bytes of the fourth transfer have dummy data.
Buffer Size Calculations
The DMA does not update the size fields in the transmit and receive descriptors. The DMA updates only
the status fields (RDES and TDES) of the descriptors. The driver must perform the size calculations.
The transmit DMA transfers the exact number of bytes (indicated by the buffer size field of TDES1) to the
MAC. If a descriptor is marked as th first (FS bit of TDES1 is set), then the DMA marks the first transfer
from the buffer as the start of frame. If a descriptor is marked as the last (LS bit of TDES1), then the DMA
marks the last transfer from that data buffer as the end-of-frame to the MTL.
The receive DMA transfers data to a buffer until the buffer is full or the end-of-frame is received from the
MTL. If a descriptor is not marked as the last (LS bit of RDES0), then the descriptor's corresponding
buffer(s)​ are full and the amount of valid data in a buffer is accurately indicated by its buffer size field
minus the data buffer pointer offset when the FS bit of that descriptor is set. The offset is zero when the
data buffer pointer is aligned to the data bus width. If a descriptor is marked as the last, then the buffer
may not be full (as indicated by the buffer size in RDES1). To compute the amount of valid data in this
final buffer, the driver must read the frame length (FL bits of RDES0[29:16]) and subtract the sum of the
buffer sizes of the preceding buffers in this frame. The receive DMA always transfers the start of next
frame with a new descriptor.
Note: Even when the start address of a receive buffer is not aligned to the data width of system bus, the
system should allocate a receive buffer of a size aligned to the system bus width. For example, if the
system allocates a 1,024-byte (1 KB) receive buffer starting from address 0x1000, the software can
program the buffer start address in the receive descriptor to have a 0x1002 offset. The receive DMA
writes the frame to this buffer with dummy data in the first two locations (0x1000 and 0x1001). The
actual frame is written from location 0x1002. Thus, the actual useful space in this buffer is 1,022
bytes, even though the buffer size is programmed as 1,024 bytes, because of the start address offset.
Transmission
The DMA can transmit with or without an optional second frame (OSF).
Related Information
Transmit Descriptor
TX DMA Operation: Default (Non-OSF) Mode
The transmit DMA engine in default mode proceeds as follows:
1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit (TDES0[31]) after
setting up the corresponding data buffer(s)​ with Ethernet frame data.
2. When Bit 13 (ST) of Register 6 (Operation Mode Register) is set, the DMA enters the Run state.
3. While in the Run state, the DMA polls the transmit descriptor list for frames requiring transmission.
After polling starts, it continues in either sequential descriptor ring order or chained order. If the DMA
detects a descriptor flagged as owned by the Host (TDES0[31] = 0), or if an error condition occurs,
transmission is suspended and both the Bit 2 (Transmit Buffer Unavailable) and Bit 16 (Normal
Interrupt Summary) of the Register 5 (Status Register) are set. The transmit Engine proceeds to
4. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA decodes the
transmit Data Buffer address from the acquired descriptor.
Ethernet Media Access Controller
Send Feedback
on page 17-29
Example: Buffer Write
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17-19
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step 9.
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