Altera cyclone V Technical Reference page 1241

17-26
Reception
Figure 17-8: Receive DMA Operation
Set Descriptor
When software has enabled timestamping through the
Control Register) and a valid timestamp value is not available for the frame (for example, because
the receive FIFO buffer was full before the timestamp could be written to it), the DMA writes all
ones to RDES2 and RDES3 descriptors . Otherwise (that is, if timestamping is not enabled), the
RDES2 and RDES3 descriptors remain unchanged.
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Own Bit
no no
Flush
Set For Next
Disabled?
Descriptor?
yes
yes
Close RDES0 As
Intermediate Descriptor
Error
Start
Rx DMA
Poll Demand/
New Frame Available
(Re-)Fetch Next
Descriptor
Rx DMA
Error?
Suspended
no
yes
Frame
no
Transfer Own Bit Set?
Complete?
yes
no
yes Flush
Frame Data
Disabled?
Available?
no yes
Write Data
Flush the
Remaining Frame to Buffer(s)
no
Fetch Next
Error?
Descriptor
Error?
no
Frame
no yes
Timestamp
Transfer
Present?
Complete?
no
Close RDES0 As
Last Descriptor
no
Error?
yes
bit of register 448 (Timestamp
tsena
Start
Stop
Rx DMA
yes
no
Wait for Frame
Data
yes
yes
Write Timestamp
to RDES2 & RDES3
no
Error?
Ethernet Media Access Controller
cv_5v4
2016.10.28
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