Altera cyclone V Technical Reference page 1232

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

cv_5v4
2016.10.28
A data buffer resides in the Host physical memory space, and consists of an entire frame or part of a frame,
but cannot exceed a single frame. Buffers contain only data, buffer status is maintained in the descriptor.
Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span
multiple frames. The DMA skips to the next frame buffer when end-of-frame is detected. Data chaining
can be enabled or disabled.
Figure 17-4: Descriptor Ring Structure
Figure 17-5: Descriptor Chain Structure
Ethernet Media Access Controller
Send Feedback
Descriptor 0
Descriptor 0
Descriptor 1
Descriptor 2
Descriptor n
Descriptor 0
Descriptor 1
Descriptor 2
Next Descriptor
Descriptor Lists and Data Buffers
Buffer 1
Buffer 1
Buffer 2
Buffer 1
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 1
Buffer 1
17-17
Altera Corporation

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents