Altera cyclone V Technical Reference page 1255

17-40
Receive Descriptor Field 1 (RDES1)
0
Related Information
Receive Descriptor Field 4 (RDES4)
•
Receive Descriptor Field 6 (RDES6)
•
Receive Descriptor Field 7 (RDES7)
•
Receive Descriptor Field 1 (RDES1)
Table 17-12: Receive Descriptor Field 1 (RDES1)
Bit
31 DIC: Disable Interrupt on Completion
When set, this bit prevents setting the Status Register's RI bit (CSR5[6]) for the received frame
ending in the buffer indicated by this descriptor. As a result, the RI interrupt for the frame is
disabled and is not asserted to the Host.
30:29 Reserved
28:16 RBS2: Receive Buffer 2 Size
These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4,
even if the value of RDES3 (buffer2 address pointer) in the Receive Descriptor Field 3 (RDES3)
is not aligned to the bus width. If the buffer size is not an appropriate multiple of 4, the
resulting behavior is undefined. This field is not valid if RDES1[14] is set. For more information
about calculating buffer sizes, refer to the Buffer Size Calculations section in this chapter.
15 RER: Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns
to the base address of the list, creating a descriptor ring.
Altera Corporation
Bit
Extended Status Available/RX MAC Address
When either advanced timestamp or IP Checksum Offload (Type 2)
is present, this bit, when set, indicates that the extended status is
available in descriptor word 4 (RDES4). This bit is valid only when
the Last Descriptor bit (RDES0[8]) is set.
When the Advance Timestamp Feature or IPC Full Offload is not
selected, this bit indicates RX MAC Address status. When set, this
bit indicates that the RX MAC Address registers value (1 to 15)
matched the frame's DA field. When clear, this bit indicates that the
RX MAC Address Register 0 value matched the DA field.
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Description
on page 17-42
on page 17-45
on page 17-46
Description
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†
2016.10.28
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