Altera cyclone V Technical Reference page 1249

17-34
Transmit Descriptor
Bit
11
LC: Loss of Carrier
When set, this bit indicates that a loss of carrier occurred during frame transmission (that is,
the gmii_crs_i signal was inactive for one or more transmit clock periods during frame
transmission). This bit is valid only for the frames transmitted without collision when the MAC
operates in the half-duplex mode.
10
NC: No Carrier
When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during
transmission.
9
LC: Late Collision
When set, this bit indicates that frame transmission is aborted because of a collision occurring
after the collision window (64 byte-times, including preamble, in MII mode and 512 byte-
times, including preamble and carrier extension, in GMII mode). This bit is not valid if the
Underflow Error bit is set.
8
EC: Excessive Collision
When set, this bit indicates that the transmission was aborted after 16 successive collisions
while attempting to transmit the current frame. If Bit 9 (Disable Retry) in Register 0 (MAC
Configuration Register) is set, this bit is set after the first collision, and the transmission of the
frame is aborted.
7
VF: VLAN Frame
When set, this bit indicates that the transmitted frame is a VLAN-type frame.
6:3
CC: Collision Count (Status field)​
These status bits indicate the number of collisions that occurred before the frame was
transmitted. This count is not valid when the Excessive Collisions bit (TDES0[8]) is set. The
EMAC updates this status field only in the half-duplex mode.
2
ED: Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of
over 24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo frame is enabled) if
Bit 4 (Deferral Check) bit in Register 0 (MAC Configuration Register) is set.
1
UF: Underflow Error
When set, this bit indicates that the MAC aborted the frame because the data arrived late from
the Host memory. Underflow Error indicates that the DMA encountered an empty transmit
buffer while transmitting the frame. The transmission process enters the Suspended state and
sets both Transmit Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]).
0
DB: Deferred Bit
When set, this bit indicates that the MAC defers before transmission because of the presence of
carrier. This bit is valid only in the half-duplex mode.
Altera Corporation
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Description
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2016.10.28
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