Altera cyclone V Technical Reference page 1205

16-54
Aligned Asymmetric Program with Multiple Loads
Figure 16-28: Simple Aligned Program
Each
DMALD
This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four
MFIFO buffer entries.
Aligned Asymmetric Program with Multiple Loads
The following program performs four loads for each store and the source address and destination address
are aligned with the AXI data bus width.
DMAMOV CCR, SB1 SS64 DB4 DS64
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4000
DMALP 16
DMALD
DMALD ; shown as b in the figure below
DMALD ; shown as c in the figure below
DMALD ; shown as d in the figure below
DMAST ; shown as e in the figure below
DMALPEND
DMAEND
Figure 16-29: Aligned Asymmetric Program with Multiple Loads
Each
DMALD
This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four
MFIFO buffer entries.
Altera Corporation
requires four entries and each
4 a a a
0
b b
; shown as a in the figure below
requires one entry and each
d d
4
c c
b b
a a
0
e e
removes four entries.
DMAST
Data from
DMALD
a 7
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
Data for
b b
DMAST
removes four entries.
DMAST
Data from
4x DMALD
d
c
b
a
e
Data for
DMAST
DMALD
0
DMAST
DMALD
7 0
a a a a a a a a
b b b b b b b b
c c c c c c c c
d d d d d d d d
DMAST
cv_5v4
2016.10.28
DMA Controller
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