Altera cyclone V Technical Reference page 1212

Hard processor system
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cv_5v4
2016.10.28
Figure 16-36: DMAC Summary Register Map
DMA Controller
Send Feedback
DMA Controller Address Map and Register Definitions
Component ID
Configuration
Debug
AXI and Loop Counter Status
DMA Channel Thread Status
Control
0xFFC
0xFE0
0xE80
0xE00
0xD0C
0xD00
0x4FC
0x400
0x13C
0x100
0x05C
0x000
Altera Corporation
16-61

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