Altera cyclone V Technical Reference page 1225

17-10
FPGA EMAC I/O Signals
emac_phy_rxd_i[7:0]
emac_phy_rxdv_i
emac_phy_rxer_i
emac_rst_clk_rx_n_o
emac_phy_crs_i
emac_phy_col_i
Related Information
EMAC FPGA Interface Initialization
Information on how to initialize GMII/MII interface
Altera Corporation
Signal Name
PHY Receive Data
PHY Receive Data
Valid
PHY Receive Error
Receive clock reset
output.
PHY Carrier Sense
PHY Collision Detect
In/Out Width
In 8
In 1
In 1
Out 1
In 1
In 1
on page 17-65
Description
This is an eight-bit receive data
bus from the PHY. In GMII
mode, all eight bits are sampled.
The validity of the data is
qualified with
phy_rxdv_i
. For lower speed
phy_rxer_i
MII operation, only bits [3:0] are
sampled. These signals are
synchronous to
phy_clk_rx_i
This signal is driven by PHY. In
GMII mode, when driven high, it
indicates that the data on the
bus is valid. It remains
phy_rxd
asserted continuously from the
first recovered byte of the frame
through the final recovered byte.
This signal indicates an error or
carrier extension (GMII) in the
received frame. This signal is
synchronous to
phy_clk_rx_i
Receive clock reset output.
The reset pulse width of the
signal is three
rst_clk_rx_n_o
transmit clock cycles.
This signal is asserted by the PHY
when either the transmit or
receive medium is not idle. The
PHY de-asserts this signal when
both transmit and receive
interfaces are idle. This signal is
not synchronous to any clock.
This signal, valid only when
operating in half duplex, is
asserted by the PHY when a
collision is detected on the
medium. This signal is not
synchronous to any clock.
Ethernet Media Access Controller
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cv_5v4
2016.10.28
and
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