Altera cyclone V Technical Reference page 1210

cv_5v4
2016.10.28
DMAMOV DAR, 0x4004
DMALP 16
DMALD ; shown as a in the figure below
DMAST ; shown as b in the figure below
DMALPEND
DMAEND
Figure 16-34: Aligned Burst with Unaligned MFIFO Buffer Width
In this example, the destination address is not 64-bit aligned, it requires three rather than the expected two
MFIFO buffer entries.
This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of three
MFIFO buffer entries.
Fixed Transfers
Fixed Destination with Aligned Address
In this program, the source address and destination address are aligned with the AXI data bus width, and
the destination address is fixed.
DMAMOV CCR, SB2 SS64 DB4 DS32 DAF
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4000
DMALP 16
DMALD ; shown as a in the figure below
DMAST ; shown as b in the figure below
DMALPEND
DMAEND
DMA Controller
Send Feedback
3 a a a a
0 b b b
Data from DMALD
DMALD
7
a a a a
a a a a a a a a
Data for
b DMAST
DMAST
Fixed Transfers
a a a a
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