Altera cyclone V Technical Reference page 1259

Hard processor system
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17-44
Receive Descriptor Field 4 (RDES4)
Bit
11:8
Message Type
These bits are encoded to give the type of the message received.
• 0000: No PTP message received
• 0001: SYNC (all clock types)
• 0010: Follow_Up (all clock types)
• 0011: Delay_Req (all clock types)
• 0100: Delay_Resp (all clock types)
• 0101: Pdelay_Req (in peer-to-peer transparent clock)
• 0110: Pdelay_Resp (in peer-to-peer transparent clock)
• 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
• 1000: Announce
• 1001: Management
• 1010: Signaling
• 1011-1110: Reserved
• 1111: PTP packet with Reserved message type
7
IPv6 Packet Received
When set, this bit indicates that the received packet is an IPv6 packet. This bit is updated only
when Bit 10 (IPC) of Register 0 (MAC Configuration Register) is set.
6
IPv4 Packet Received
When set, this bit indicates that the received packet is an IPv4 packet. This bit is updated only
when Bit 10 (IPC) of Register 0 (MAC Configuration Register) is set.
5
IP Checksum Bypassed
When set, this bit indicates that the checksum offload engine is bypassed.
4
IP Payload Error
When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or
ICMP checksum) that the EMAC calculated does not match the corresponding checksum field
in the received segment. It is also set when the TCP, UDP, or ICMP segment length does not
match the payload length value in the IP Header field. This bit is valid when either Bit 7 or Bit 6
is set.
3
IP Header Error
When set, this bit indicates that either the 16-bit IPv4 header checksum calculated by the
EMAC does not match the received checksum bytes, or the IP datagram version is not
consistent with the Ethernet Type value. This bit is valid when either Bit 7 or Bit 6 is set.
Altera Corporation
Description
2016.10.28
Ethernet Media Access Controller
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cv_5v4

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