Altera cyclone V Technical Reference page 1204

cv_5v4
2016.10.28
When a program specifies that incrementing transactions are to be performed to the destination, the
DMAC packs data into the MFIFO buffer to minimize the usage of the MFIFO buffer entries. For example,
the DMAC packs two 32-bit words into a single entry in the MFIFO buffer when the program uses a
source address of 0x100, and destination address of 0x200.
The number of entries required to store the data loaded from a source is not a simple calculation of
amount of source data divided by MFIFO buffer width in the following situations:
• The source address is not aligned to the AXI bus width.
• The destination address is not aligned to the AXI bus width.
• The transactions are to a fixed destination, that is, a non-incrementing address.
The
DMALD
data transferred by an AXI transaction depends on the values programmed in to the
address of the transaction.
The following sections provide several example DMAC programs together with illustrations of the MFIFO
buffer usage.
Note: These sections show MFIFO buffer usage in the following ways:
• A graph of the number of MFIFO buffer entries versus time
• A diagram of the byte-lane manipulation that the DMAC performs when data enters the MFIFO
buffer.
Note: The numbers 0 and 7 in the MFIFO buffer diagrams indicate the byte lanes in the MFIFO buffer.
Related Information
ARM Information Center
Information about unaligned transfers available from the ARM Infocenter website.
Aligned Transfers
Simple Aligned Program
The following program shows the MFIFO buffer usage. In this program, the source address and destina‐
tion address are aligned with the AXI data bus width.
DMAMOV CCR, SB4 SS64 DB4 DS64
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4000
DMALP 16
DMALD
DMALPEND
DMAEND
DMA Controller
Send Feedback
and instructions each specify that an AXI transaction is to be performed. The amount of
DMAST
; shown as a in figure below
DMAST ; shown as b in figure below
16-53
Aligned Transfers
register and the
CCR n
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