Altera cyclone V Technical Reference page 1182

cv_5v4
2016.10.28
A discontinuity occurs if you change any of the following:
•
endian_swap_size
•
dst_inc
•
dst_burst_size
• register so that it modifies the destination byte lane alignment. Because the bus width is 64 bits,
DARn
you change bits [2:0] in the
When a discontinuity in the destination data stream occurs, the DMAC:
1. Halts execution of the DMA channel thread.
2. Completes all outstanding read and write operations for the channel. That is, as if the DMAC were
executing
3. Discards any residual MFIFO buffer data for the channel.
4. Resumes execution of the DMA channel thread.
Updates that affect the source address
If you use a
cycle, then this might cause a discontinuity in the source data stream.
A discontinuity occurs if you change any of the following:
•
src_inc
•
src_burst_size
• register so that it modifies the source byte lane alignment. Because the bus width is 64 bits, you
SAR
change bits [2:0] in the
When a discontinuity in the source data stream occurs, the DMAC:
1. Halts execution of the DMA channel thread.
2. Completes all outstanding read operations for the channel. That is, as if the DMAC were executing
DMARMB
3. Resumes execution of the DMA channel thread. No data is discarded from the MFIFO buffer.
Resource Sharing Between DMA Channels
DMA channel programs share the MFIFO buffer data storage resource. You must not start a set of
concurrently running DMA channel programs with a resource requirement that exceeds 512, the size of
the MFIFO buffer. If you exceed this limit, then the DMAC might lock up and generate a Watchdog abort.
Refer to the "Watchdog Abort" section for more information regarding the abort mechanism.
The DMAC includes a mechanism called the load-lock to ensure that the shared MFIFO buffer resource is
used correctly. The load-lock is either owned by one channel or it is free. The channel that owns the
load-lock can execute
a instruction until it takes ownership of the load-lock.
DMALD
A channel claims ownership of the load-lock when:
• It executes a
• No other channel currently owns the load-lock
DMA Controller
Send Feedback
field.
bit.
field when
dst_inc
register.
DARn
and .
DMARMB DMAWMB
instruction to update the
DMAMOV
bit.
field.
register.
SAR
instructions successfully. A channel that does not own the load-lock pauses at
DMALD
or instruction
DMALD DMALDP
Updates that affect the source address
= 0, that is, fixed-address burst.
register or
SARn CCRn
register part way through a DMA
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