Altera cyclone V Technical Reference page 1247

17-32
Transmit Descriptor
Bit
26 DP: Disable Pad
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes.
When this bit is cleared, the DMA automatically adds padding and CRC to a frame shorter
than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This bit
is valid only when the first segment (TDES0[28]) is set.
25 TTSE: Transmit Timestamp Enable
When set, this bit enables IEEE1588 hardware timestamping for the transmit frame referenced
by the descriptor. This field is valid only when the First Segment control bit (TDES0[28]) is set.
24 Reserved
23:22
CIC: Checksum Insertion Control. These bits control the checksum calculation and insertion.
The following list describes the bit encoding:
■ 0x0: Checksum insertion disabled.
■ 0x1: Only IP header checksum calculation and insertion are enabled.
■ 0x2: IP header checksum and payload checksum calculation and insertion are enabled, but
pseudoheader checksum is not calculated in hardware.
■ 0x3: IP Header checksum and payload checksum calculation and insertion are enabled, and
pseudoheader checksum is calculated in hardware.
This field is valid when the First Segment control bit (TDES0[28]) is set.
21 TER: Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns
to the base address of the list, creating a descriptor ring.
20
TCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next descriptor
address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is
a "don't care" value.
TDES0[21] takes precedence over TDES0[20].
19:18
Reserved
17
TTSS: Transmit Timestamp Status
This field is used as a status bit to indicate that a timestamp was captured for the described
transmit frame. When this bit is set, TDES2 and TDES3 have a timestamp value captured for
the transmit frame. This field is only valid when the descriptor's Last Segment control bit
(TDES0[29]) is set.
Altera Corporation
Description
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Ethernet Media Access Controller
cv_5v4
2016.10.28
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