Altera cyclone V Technical Reference page 1257

17-42
Receive Descriptor Field 3 (RDES3)
Receive Descriptor Field 3 (RDES3)
Table 17-14: Receive Descriptor Field 3 (RDES3)
Bit
31:0
Related Information
Host Data Buffer Alignment
•
Receive Descriptor Field 1 (RDES1)
•
Receive Descriptor Field 4 (RDES4)
The extended status is written only when there is status related to IPC or timestamp available. The
availability of extended status is indicated by Bit 0 in RDES0. This status is available only when the
Advance Timestamp or IPC Full Offload feature is selected.
Table 17-15: Receive Descriptor Field 4 (RDES4)
Bit
31:28 Reserved
27:26 Layer 3 and Layer 4 Filter Number Matched
These bits indicate the number of the Layer 3 and Layer 4 Filter that matched the received
frame.
• 00: Filter 0
• 01: Filter 1
• 10: Filter 2
• 11: Filter 3
This field is valid only when Bit 24 or Bit 25 is set. When more than one filter matches, these
bits give only the lowest filter number.
Altera Corporation
Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when a descriptor ring structure is
used. If the Second Address Chained (RDES1[14]) bit in Receive Descriptor Field 1
(RDES1) is set, this address contains the pointer to the physical memory where the Next
descriptor is present.
If RDES1[14], in the Receive Descriptor Field 1 (RDES1) is set, the buffer (Next
descriptor) address pointer must be bus width-aligned (RDES3[1:0] = 0. LSBs are ignored
internally.) However, when RDES1[14] in the Receive Descriptor Field 1 (RDES1) is
cleared, there are no limitations on the RDES3 value, except for the following condition:
the DMA uses the value programmed in RDES3 [1:0] for its buffer address generation
when the RDES3 value is used to store the start of frame. The DMA ignores RDES3 [1:0]
if the address pointer is to a buffer where the middle or last part of the frame is stored.
on page 17-18
†
Description
on page 17-40
Description
†
2016.10.28
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