Cortex-A9 Mpu Subsystem Components; Cortex-A9 Mpcore - Altera Cyclone V Device Handbook

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Cortex-A9 MPU Subsystem Components

Cortex-A9 MPU Subsystem Components
The Altera Cortex-A9 MPU subsystem consists of the following hardware blocks:
• ARM Cortex-A9 MPCore
• ARM L2C-310 L2 cache controller
• ACP ID mapper
• Debugging and trace features

Cortex-A9 MPCore

The MPU subsystem includes a stand-alone, full-featured ARM Cortex-A9 MPCore single- or dual-core
32-bit application processor. The processor, like other HPS masters, can access IP in the FPGA fabric through
the HPS-to-FPGA bridges.
Functional Description
The ARM Cortex-A9 MPCore contains the following blocks:
• One or two Cortex-A9 Revision r3p0 processors operating in SMP or AMP mode
• Snoop control unit (SCU)
• Private interval timer for each processor core
• Private watchdog timer for each processor core
• Global timer
• Interrupt controller
Each transaction originating from the Altera Cortex-A9 MPU subsystem can be flagged as secure or nonsecure.
Implementation Details
Table 6-1: Cortex-A9 MPCore Processor Configuration
This table shows the parameter settings for the Altera Cortex-A9 MPCore.
Cortex-A9 processors
Instruction cache size per Cortex-A9 processor
Data cache size per Cortex-A9 processor
TLB size per Cortex-A9 processor
Media Processing Engine with NEON
per Cortex-A9 processor
Preload Engine per Cortex-A9 processor
Number of entries in the Preload Engine FIFO per
Cortex-A9 processor
(4)
Includes support for floating-point operations.
Altera Corporation
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128 entries
Included
Included
16
Cortex-A9 Microprocessor Unit Subsystem
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2013.12.30