Altera cyclone V Technical Reference page 1289

17-74
EMAC Module Address Map
Register
MAC_Address9_High
page 17-205
MAC_Address9_Low
page 17-209
MAC_Address10_High
page 17-209
MAC_Address10_Low
page 17-213
MAC_Address11_High
page 17-213
MAC_Address11_Low
page 17-217
MAC_Address12_High
page 17-217
MAC_Address12_Low
page 17-221
MAC_Address13_High
page 17-221
MAC_Address13_Low
page 17-225
MAC_Address14_High
page 17-225
MAC_Address14_Low
page 17-229
MAC_Address15_High
page 17-229
MAC_Address15_Low
page 17-233
SGMII_RGMII_SMII_Cont
rol_Status on page
17-233
MMC_Control
17-235
MMC_Receive_Interrupt
on page 17-237
MMC_Transmit_Interrup
t on page 17-243
MMC_Receive_Interrupt
_Mask on page 17-249
Altera Corporation
Offset
on 0x88
on 0x8C
on 0x90
on 0x94
on 0x98
on 0x9C
on 0xA0
on 0xA4
on 0xA8
on 0xAC
on 0xB0
on 0xB4
on 0xB8
on 0xBC
0xD8
on page 0x100
0x104
0x108
0x10C
Width Acces Reset Value
s
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RW 0xFFFF
32 RW 0xFFFFFFFF
32 RO 0x0
32 RW 0x0
32 RO 0x0
32 RO 0x0
32 RW 0x0
Description
Register 34 (MAC Address9 High
Register)
Register 35 (MAC Address9 Low
Register)
Register 36 (MAC Address10
High Register)
Register 37 (MAC Address10 Low
Register)
Register 38 (MAC Address11
High Register)
Register 39 (MAC Address11 Low
Register)
Register 40 (MAC Address12
High Register)
Register 41 (MAC Address12 Low
Register)
Register 42 (MAC Address13
High Register)
Register 43 (MAC Address13 Low
Register)
Register 44 (MAC Address14
High Register)
Register 45 (MAC Address14 Low
Register)
Register 46 (MAC Address15
High Register)
Register 47 (MAC Address15 Low
Register)
Register 54 (SGMII/RGMII/SMII
Status Register)
Register 64 (MMC Control
Register)
Register 65 (MMC Receive
Interrupt Register)
Register 66 (MMC Transmit
Interrupt Register)
Register 67 (MMC Receive
Interrupt Mask Register)
Ethernet Media Access Controller
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cv_5v4
2016.10.28