Altera cyclone V Technical Reference page 1375

Hard processor system

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Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Debug Fields

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software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

When high, this bit indicates that the MTL TxStatus

FIFO is full. Therefore, the MTL cannot accept any

more frames for transmission.

When high, this bit indicates that the MTL Tx FIFO

is not empty and some data is left for transmission.

Base Address

MTL TxStatus FIFO Not Full Status

MTL TxStatus FIFO Full Status

MTL Tx FIFO Empty

MTL Tx FIFO Not Empty

Ethernet Media Access Controller

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