Altera cyclone V Technical Reference page 1310

cv_5v4
2016.10.28
LPI_Control_Status
The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The
status bits are cleared when this register is read.
LPI_Timers_Control
The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for
which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the
normal transmission.
Interrupt_Status
The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt
events are generated only when the corresponding optional feature is enabled.
Interrupt_Mask
The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding
event in the Interrupt Status Register. The interrupt signal is sbd_intr_o.
MAC_Address0_High
The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station.
The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the
MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first
column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with
0x665544332211. Because the MAC address registers are double-synchronized to the (G)MII clock
domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0]
(in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain.
MAC_Address0_Low
The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC address of the station.
MAC_Address1_High
The MAC Address1 High register holds the upper 16 bits of the 2nd 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address1_Low
The MAC Address1 Low register holds the lower 32 bits of the 2nd 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address2_High
The MAC Address2 High register holds the upper 16 bits of the 3rd 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address2 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
Ethernet Media Access Controller
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on page 17-166
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on page 17-170
on page 17-171
on page 17-172
on page 17-173
on page 17-177
on page 17-177
GMAC Register Group Register Descriptions
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