Altera cyclone V Technical Reference page 1265

17-50
Transmit Path Functions
The software must calculate the drift in frequency based on the Sync messages and update the Addend
register accordingly.
Initially, the slave clock is set with
†
follows:
FreqCompensationValue
If MasterToSlaveDelay is initially assumed to be the same for consecutive sync messages, the algorithm
described below must be applied. After a few sync cycles, frequency lock occurs. The slave clock can then
determine a precise MasterToSlaveDelay value and re-synchronize with the master using the new value.
The algorithm is as follows:
• At time
message when its local clock is
MasterClockTime
• The master clock count for current sync cycle,
MasterClockCount
(assuming that MasterToSlaveDelay is the same for sync cycles n and n – 1)
• The slave clock count for current sync cycle,
SlaveClockCount
• The difference between master and slave clock counts for current sync cycle,
†
by:
ClockDiffCount
• The frequency-scaling factor for the slave clock,
FreqScaleFactor
• The frequency compensation value for Addend register,
FreqCompensationValue
In theory, this algorithm achieves lock in one Sync cycle; however, it may take several cycles, because of
changing network propagation delays and operating conditions.
This algorithm is self-correcting: if for any reason the slave clock is initially set to a value from the master
that is incorrect, the algorithm corrects it at the cost of more Sync cycles.
Transmit Path Functions
The MAC captures a timestamp when the start-of-frame data (SFD) is sent on the PHY interface. You can
control the frames for which timestamps are captured on a per frame basis. In other words, each transmit
frame can be marked to indicate whether a timestamp should be captured for that frame.
You can use the conrol bits in the transmit descriptor to indicate whether a timestamp should be capture
for a frame. The MAC returns the timestamp to the software inside the corrsponding transmit descriptor,
Altera Corporation
†
FreqCompensationValue0
= 232 / FreqDivisionRatio
0
†
the master sends the slave clock a sync message. The slave receives this
MasterSyncTime
n
SlaveClockTime
= MasterSyncTime
n
= MasterClockTime
n
= SlaveClockTime
n
= MasterClockCount
n
= (MasterClockCount
n
= FreqScaleFactor
n
in the Addend register. This value is as
†
and computes
MasterClockTime
n
+ MasterToSlaveDelay
n
MasterClockCount
– MasterClockTime
n
is given by:
SlaveClockCount
n
– SlaveClockTime
n n-1
– SlaveClockCount
n
FreqScaleFactor
+ ClockDiffCount
n
FreqCompensationValue
× FreqCompensationValue
n
†
†
as:
n
†
n
†
is given by:
n
n-1
†
†
†
ClockDiffCount
†
n
†
is given by:
n
) / SlaveClockCount
n
is given by:
n
†
– 1
n-1
†
†
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2016.10.28
†
is given
n
†
n
†