Altera cyclone V Technical Reference page 1378

Hard processor system

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LPI_Control_Status

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The

status bits are cleared when this register is read.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Ethernet Media Access Controller

Send Feedback

When high, this field indicates the active state of the

small FIFO Read and Write controllers of the MAC

Receive Frame Controller Module.

When high, this bit indicates that the MAC GMII or

MII receive protocol engine is actively receiving data

and not in IDLE state.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Disable Active State FIFO Read Write

Enable Active State FIFO Read Write

Protocol Engine Active

Base Address

LPI_Control_Status

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