Altera cyclone V Technical Reference page 1266

cv_5v4
2016.10.28
thus connecting the timestamp automatically to the specific PTP frame. The 64-bit timestamp information
is written to the TDES2 and TDES3 fields. T
Receive Path Functions
The MAC captures the timestamp of all frames received on the PHY interface. The DMA returns the
timestamp to the software in the corresponding receive descriptor. The timestamp is written only to the
last receive descriptor.
Timestamp Error Margin
According to the IEEE1588 specifications, a timestamp must be captured at the SFD of the transmitted
and received frames at the PHY interface. Because the PHY interface receive and transmit clocks are not
synchronous to the reference timestamp clock (
a timestamp is moved between asynchronous clock domains. In the transmit path, the captured and
reported timestamp has a maximum error margin of two PTP clocks, meaning that the captured
timestamp has a reference timing source value that is occurred within two clocks after the SFD is
transmitted on the PHY interface.
Similarly, in the receive path, the error margin is three PHY interface clocks, plus up to two PTP clocks.
You can ignore the error margin due to the PHY interface clock by assuming that this constant delay is
present in the system (or link) before the SFD data reaches the PHY interface of the MAC.
Frequency Range of Reference Timing Clock
The timestamp information is transferred across asynchronous clock domains, from the EMAC clock
domain to the FPGA clock domain. Therefore, a minimum delay is required between two consecutive
timestamp captures. This delay is four PHY interface clock cycles and three PTP clock cycles. If the delay
between two timestamp captures is less than this amount, the MAC does not take a timestamp snapshot
for the second frame.
The maximum PTP clock frequency is limited by the maximum resolution of the reference time (20 ns
resulting in 50 MHz) and the timing constraints achievable for logic operating on the PTP clock. In
addition, the resolution, or granularity, of the reference time source determines the accuracy of the
synchronization. Therefore, a higher PTP clock frequency gives better system performance.
The minimum PTP clock frequency depends on the time required between two consecutive SFD bytes.
Because the PHY interface clock frequency is fixed by the IEEE 1588 specification, the minimum PTP
clock frequency required for proper operation depends on the operating mode and operating speed of the
†
MAC.
Table 17-18: Minimum PTP Clock Frequency Example
Mode
100-Mbps full-duplex
operation
Ethernet Media Access Controller
Send Feedback
†
†
Minimum Gap Between Two SFDs
168 MII clocks
(128 clocks for a 64-byte frame + 24
clocks of min IFG + 16 clocks of
preamble)
) a small amount of drift is introduced when
clk_ptp_ref
(3 * PTP) + (4 * MII) <= 168 * MII,
that is, ~0.5 MHz (168 – 4) * 40 ns ÷
3 = 2180 ns period)
Receive Path Functions
†
†
Minimum PTP Frequency
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